1. Field of the Invention
The present invention relates to a protect circuit of a register for preventing the contents of an important register from being unduly changed owing to changes in an input or output to a port due to noise or to a runaway of a program or the like in a microcomputer, and particularly to a protect circuit of a register which can implement more positive protection by adding to a conventional protect function, which is achieved by only comparing the contents in registers, a protect function using a timer.
2. Description of Related Art
FIG. 6 is a circuit diagram showing a configuration of a conventional protect circuit. In FIG. 6, the reference numeral 1 designates a data bus in a microcomputer, and 2 and 3 each designate an output register consisting of a D flit-flop. The D flip-flop 2 or 3 with its data input terminal D connected to the data bus 1 inputs and holds data "0" or "1" on the data bus 1 when a write signal .cndot.w1 or .cndot.w2 is applied to its trigger terminal T, and outputs the stored data "0" or "1" from its output terminal Q.
The reference numeral 4 designates an exclusive-NOR circuit which supplies an output gate control terminal X of a clocked inverter 5 with the inverted exclusive OR of the outputs of the output registers 2 and 3. Receiving, at its output gate control terminal X, data "1" from the exclusive-NOR circuit 4 when the output data of the output registers 2 and 3 are identical, the clocked inverter 5 opens to supply a latch 6 with the output data of the output register 2.
The latch 6 consists of inverters 7 and 8 connected in anti-parallel: The input terminal of the inverter 7 and the output terminal of the inverter 8 are connected to the output terminal of the clocked inverter 5, and the output terminal of the inverter 7 and the input terminal of the Lit inverter 8 are connected to a register no shown in FIG. 6. Thus, the latch 6 holds the data fed from the output register 2 through the clocked inverter 5, and supplies the data to the register.
Next, the operation of the conventional circuit will be described.
Let us assume that a program of the microcomputer runs normally, and identical data, for example, data "1" on the data bus 1 is held sequentially by the output registers 2 and 3 in response to the write signals .cndot.w1 and .cndot.w2 which are sequentially input. In response to the identical data "1" output from the output registers 2 and 3, the exclusive-NOR circuit 4 supplies data "1" to the output gate control terminal X of the clocked inverter 5.
This places the output terminal of the clocked inverter 5 at the open state so that the latch 6 is supplied through the clocked inverter 5 with the data "1" held in the output register 2 and holds the data. The data "1" held in the latch 6 is supplied to the register as register control data to update the contents in that register.
In contrast, when the program of the microcomputer runs away, there appears a state that the output registers 2 and 3, which have held the identical data in the normal case, hold data of different values.
Assuming that data "0" is held in the output register 2 and "1" in the output register 3, the exclusive-NOR circuit 4 outputs data "0" because of different values output from the output registers 2 and 3, and supplies the data to the output gate control terminal X of the clocked inverter 5.
This places the output terminal of the clocked inverter 5 at a closed state so that the data "0" held in the output register 2 is cut off by the clocked inverter 5. Thus, the latch 6 keeps the data "1" having been held in the normal state of the program, thereby supplying the data "1" to the register as the register control data. In this way, the register is protected.
Incidentally, as a prior art relevant to the present invention, Japanese patent application laid-open No. 2-150943/1990 is known.
The conventional protect circuit of the register with the foregoing configuration has a problem of rewriting the contents of the register in spite of the runaway of the program in the case where the time interval between the write signals .cndot.w1 and .cndot.w2 are rather long and the contents of the output registers 2 and 3 are mistakenly placed at the same value by chance.